1. Technical Field
The subject matter disclosed herein relates generally to semiconductor structures. Specifically, the subject matter disclosed herein relates to a controlled collapse chip connection (C4) and a method for forming.
2. Related Art
Controlled collapse chip connections (C4) are used to form a physical and electrical connection between semiconductor die and semiconductor packages. In conventional C4, solder is placed on a conductive pad in electrical connection with the integrated circuit (IC) of the semiconductor die, before heating the semiconductor die to bond the solder to the pad. Once heated, or “reflowed,” the solder forms a spherical shape due to the surface tension of the solder. In conventional C4 structures, spherical solder deposits are referred to as “solder bumps.” After the solder bumps are formed, the semiconductor die containing the solder bumps are bonded to the semiconductor package to complete the semiconductor device.
In forming conventional C4, the solder bumps should be uniform in shape (e.g., height, diameter). However, during the reflow process, the shape of the solder bumps often becomes inconsistent, resulting in conductivity issues between the semiconductor die and package. For example, when the heights of the solder bumps are inconsistent, the shorter solder bumps of the die may not create a complete physical or electrical connection with the package. Modifying defective solder bumps by removing or adding solder causes a change in the diameter and density of the defective solder bump, and often does not solve conductivity issues. Conventionally, defective solder bumps are identified and replaced as a whole. Replacing the defective solder bumps creates increased costs and manufacturing time when creating semiconductor devices.
Additionally, conventional C4 typically arrange the solder bumps in limited geometric configurations. More specifically, conventional C4 is arranged by a predetermined set of columns and rows. As a result of the semiconductor die having a limited contact configuration of the solder bumps, the contact configuration of the semiconductor package is also limited. These limitations in the contact configurations of the solder bumps make designing contact configurations for complex circuitry and/or complex semiconductors both difficult and time intensive.